1. Field of the Invention
The present invention relates to a semiconductor memory device and manufacturing method thereof.
2. Related Art
A floating body cell (FBC) memory device is superior in size reduction to a 1-transistor-1-capacitor (1T-1C) dynamic random-access memory (DRAM) device. Therefore, attention has been paid to the FBC memory device as a semiconductor memory device to replace the conventional 1T-1C DRAM device.
A memory cell of the FBC memory device (hereinafter, “FBC” or “memory cell”) normally consist of a MISFET formed on an SOI substrate. In an FBC, a source region, a drain region, and a body region are formed on an SOI layer. The body region put between the source region and the drain region is in an electrically floating state.
A drain current is changed according to the number of holes accumulated in the body region. It is possible to discriminate data “1” from data “0” according to a change amount of the drain current. For instance, data is discriminated as “1” when the number of holes in the body region is large, and data is discriminated as “0” when the number of holes in the body region is small. In such an FBC, if the SOI layer on which the body region is formed is made thinner, the difference in amount of signal between the data “0” and the data “1” normally becomes greater.
However, if the SOI layer is thinner, the source and drain regions are thinner, accordingly. This disadvantageously narrows a contact area between a silicide layer and the source or drain, and increases a contact resistance therebetween. For these reasons, it is disadvantageously difficult to set the difference in amount of signal between the data “0” and the data “1” sufficiently great in the conventional FBC.